1. Field of the Invention
The present invention relates in general to the detection of data input/output states of a first-in first-out (referred to hereinafter as FIFO) memory, and more particularly to a data input/output state detection apparatus which is applicable to a plurality of FIFO memories, detects the data input/output states more accurately and is simple in the construction.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional apparatus for detecting data input/output states of an FIFO memory. As shown in this drawing, the conventional data input/output state detection apparatus comprises a write counter 101 for performing a counting operation for a write clock signal WC and a write clock bar signal WCB in response to a write reset signal WR and outputting the resultant count values WQ and WQN, a read counter 102 for performing a counting operation for a read clock signal RC and a read clock bar signal RCB in response to a read reset signal RR and outputting the resultant count values RQ and RQN, a first subtracter 103 for inputting the count value RQN from the read counter 102 and the count value WQ from the write counter 101, subtracting the inputted count value RQN from the inputted count value WQ and outputting the resultant value, comparators 105-107 for comparing an output value from the first subtracter 103 with predetermined values PHF, PAF and PF and outputting the resultant signals, respectively, a clock generator 115 for generating a clock signal in response to the write clock signal WC, the write reset signal WR, the read clock bar signal RCB and the read reset signal RR and outputting the generated clock signal, and flip-flops 110-112 for latching output signals from the comparators 105-107 in response to the clock signal from the clock generator 115 and outputting the latched signals as flag signals HFF, AFF and FF, respectively.
The conventional data input/output state detection apparatus also comprises a second subtracter 104 for inputting the count value RQ from the read counter 102 and the count value WQN from the write counter 101, subtracting the inputted count value RQ from the inputted count value WQN and outputting the resultant value, comparators 108 and 109 for comparing an output value from the second subtracter 104 with predetermined values PE and PAE and outputting the resultant signals, respectively, a clock generator 116 for generating a clock signal in response to the write clock bar signal WCB, the write reset signal WR, the read clock signal RC and the read reset signal RR and outputting the generated clock signal, and flip-flops 113 and 114 for latching output signals from the comparators 108 and 109 in response to the clock signal from the clock generator 116 and outputting the resultant logic signals, respectively.
Further, the conventional data input/output state detection apparatus comprises an inverter 117 for inverting the logic signal from the flip-flop 113 and outputting the resultant flag signal EF, and an inverter 118 for inverting the logic signal from the flip-flop 114 and outputting the resultant flag signal AEF.
The operation of the conventional data input/output state detection apparatus with the above-mentioned construction will hereinafter be described.
At an initial state of an FIFO memory system, the write and read counters 101 and 102 are initialized in response to the write and read reset signals WR and RR, respectively.
Thereafter, when data input or write and output or read operations are performed by the FIFO memory, the write clock signal WC and the write clock bar signal WCB are applied for the data write operation of the FIFO memory. The count value of the write counter 101 is incremented by one whenever each of the write clock signal WC and the write clock bar signal WCB is applied. The count value of the write counter 101 indicates the number of data written into the FIFO memory up to now. Also, the read clock signal RC and the read clock bar signal RCB are applied for the data read operation of the FIFO memory. The count value of the read counter 102 is incremented by one whenever each of the read clock signal RC and the read clock bar signal RCB is applied. The count value of the read counter 102 indicates the number of data read from the FIFO memory up to now.
The write counter 101 outputs the two count values WQ and WQN, the former being varied at a rising edge of the write clock signal WC and the latter being varied at a falling edge of the write clock bar signal WCB. Similarly, the read counter 102 outputs the two count values RQ and RQN, the former being varied at a rising edge of the read clock signal RC and the latter being varied at a falling edge of the read clock bar signal RCB.
Then, the first subtracter 103 obtains a difference WQ-RQN between the count value RQN from the read counter 102 and the count value WQ from the write counter 101. The difference WQ-RQN from the first subtracter 103 indicates the number of data remaining in the FIFO memory at a time point that the write operation of the FIFO memory is started after the read operation thereof is ended.
The comparator 107 compares the output value from the first subtracter 103 with the predetermined value PF to discriminate whether it is smaller than the predetermined value PF. As a result of the comparison, the comparator 107 outputs a logic signal to the flip-flop 112. The flip-flop 112 latches the logic signal from the comparator 107 and then outputs the latched logic signal as the flag signal FF.
The comparator 106 compares the output value from the first subtracter 103 with the predetermined value PAF to discriminate whether it is smaller than the predetermined value PAF. As a result of the comparison, the comparator 106 outputs a logic signal to the flip-flop 111. The flip-flop 111 latches the logic signal from the comparator 106 and then outputs the latched logic signal as the flag signal AFF. Also, the comparator 105 compares the output value from the first subtracter 103 with the predetermined value PHF to discriminate whether it is smaller than the predetermined value PHF. As a result of the comparison, the comparator 105 outputs a logic signal to the flip-flop 110. The flip-flop 110 latches the logic signal from the comparator 105 and then outputs the latched logic signal as the flag signal HFF.
At this time, the clock generator 115, as a deglitch circuit, generates a clock pulse after a desired delay time in such a manner that the flip-flops 110-112 can latch the output signals from the comparators 105-107 at a proper time.
Here, the comparator 105 is a half full comparison block, the comparator 106 is an almost full comparison block and the comparator 107 is a full comparison block.
On the other hand, the second subtracter 104 obtains a difference WQN-RQ between the count value RQ from the read counter 102 and the count value WQN from the write counter 101. The difference WQN-RQ from the second subtracter 104 indicates the number of data remaining in the FIFO memory at a time point that the read operation of the FIFO memory is started after the write operation thereof is ended.
Then, the comparator 109 compares the output value from the second subtracter 104 with the predetermined value PAE to discriminate whether it is smaller than the predetermined value PAE. As a result of the comparison, the comparator 109 outputs a logic signal to the flip-flop 114. The flip-flop 114 latches the logic signal from the comparator 109 and outputs the latched logic signal to the inverter 118. The output signal from the flip-flop 114 is inverted by the inverter 118 and then outputted as the flag signal AEF.
The comparator 108 compares the output value from the second subtracter 104 with the predetermined value PE to discriminate whether it is smaller than the predetermined value PE. As a result of the comparison, the comparator 108 outputs a logic signal to the flip-flop 113. The flip-flop 113 latches the logic signal from the comparator 108 and outputs the latched logic signal to the inverter 117. The output signal from the flip-flop 113 is inverted by the inverter 117 and then outputted as the flag signal EF.
At this time, the clock generator 116, as a deglitch circuit, generates a clock pulse after a desired delay time in such a manner that the flip-flops 113 and 114 can latch the output signals from the comparators 108 and 109 at a proper time.
Here, the comparator 108 is an empty comparison block and the comparator 109 is an almost empty comparison block.
However, the above-mentioned conventional data input/output state detection apparatus has a disadvantage in that it cannot detect the data input/output states of a plurality of FIFO memories. Also, the comparators are provided correspondingly to respective fullness levels. For this reason, as the fullness levels are increased in number, the comparators are increased in number. The increase in the number of the comparators makes the circuit construction complex and an intentional increase in the number of the fullness levels difficult. Further, the fullness levels cannot be varied in operation, so that the data input/output states of the FIFO memory cannot be detected accurately. Moreover, the use of the deglitch circuits may result in a faulty operation in an actual manufacturing process.